3D integration

Convergence of 3D integrated packaging and 3D TSV ICs
Executive Overview
As fan-out technology production ramps and exposure to the technology grows in the industry, there is an interesting set of opportunities emerging. Although RCP technology can provide distinct advantages over both wirebond and flip chip single die packaging solutions, a closer evaluation of fan-out suggests that a more pronounced advantage is possible in the form of a multi-die, or system-in-package (SiP) solution. The RCP multi-die program is specifically designed to incorporate several of these advantages: heterogeneneous integration (die, passives, peripherals), system miniaturization, system performance, system cost, high speed in package computing, system flexibility (chip sourcing, integration), block testability, and a path to integrating with 3D TSV ICs.
Navjot Chhabra, Freescale Semiconductor, Austin, Texas, USA
Beginning in the 1990s and coming into its own in early 2000s, three dimensional (3D) through silicon via TSV IC technology has demanded a significant amount of attention. It became apparent as process and design rules continued to migrate down Moore's law that the challenges of having robust materials and chip performance were becoming a significant concern. Some of the motivations driving the development of 3D IC and TSV technologies are the increasing on-chip, high-speed signal paths as well as utilizing optimum functional blocks within the chip design. While die-to-die interconnects address many of the device functionality challenges, a number of processibility and reliability concerns remain. The hurdles to 3D integration begin with the design and modeling infrastructure and continue with clear needs for process and materials development, decreasing costs through improved yields and, ultimately, alleviating ongoing reliability concerns.
Fan-out technology
There is another technology path emerging in the industry. Similar to the evolution of front-end wafer processing, package technologies are also evolving. Historically, the motivation behind the typical packaging roadmap has been driven by the need to meet decreasing package sizes (x,y,z), lower costs, increase performance, and provide different reliability requirements and thermal and electrical compliance. However, within each packaging category the challenges of meeting certain reliability grades and functionality still remain. Similar to the ‘red brick wall' seen on the ultra-low-k material roadmap, wire bond technology is beginning to see that similar concern. As die technology keeps advancing and more functionality is required, the ability to route signals without impacting performance and cost is a great concern. While the overall die cost continues to decrease with advancing nodes, package costs are heading in the opposite direction.
In the 1980s, companies began the development of fan-out packaging technology. The idea was to eliminate the need for substrates and gold wirebond, two of the highest cost items in a package bill of materials while, at the same time, addressing some of the limitations of contemporary packaging. In 2007, Freescale introduced a fan-out technology called the redistributed chip package (RCP) built on a 300mm tool set. This specific technology is targeted at meeting the requirements listed below.
Package size reduction: ~30% size and thickness reduction vs. PBGA; package size and routability: one to six signal redistribution metal layers (RDL) and a package size ranging from 2x2mm, to as large at 40x40mm; yields: assembly yield comparable to today's packages; a cost-competitive, high productivity, large area batch process that eliminates the package substrate and eliminates gold wire bonds/C4 bumps; high-performance package with electroplated copper interconnects, reduced electrical parasitics, improved device efficiencies, higher frequency response, and active structures in routing (shielding, inductors); ultralow-k compatible (<90nm